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Device Overview S12XS Family
Accessing the reserved area in the range of 0x0C00 to 0x0FFF will return unde?ned data values.
A CPU access to any unimplemented space causes an illegal address reset.
The range between 0x10_0000 and 0x13_FFFF is mapped to DFLASH (Data Flash). The DFLASH block
sizes are listed in Table 1-2 .
Table 1-2. Derivative Dependent Memory Parameters of Device Internal Resources
Device
S12XS256
S12XS128
FLASH_LOW
0x7C_0000
0x7E_0000
SIZE/
PPAGE 1
256K / 16
128K / 8
RAM_LOW
0x0F_D000
0x0F_E000
SIZE/
RPAGE 2
12K / 3
8K / 2
DF_HIGH
0x10_1FFF
0x10_1FFF
SIZE/
EPAGE 3
8K / 8
8K / 8
S12XS64 0x7F_0000 64K / 4 0x0F_F000 4K / 1 0x10_0FFF
4K / 4
1
Number of 16K pages addressable via PPAGE register
2 Number of 4K pages addressing the RAM via PPAGE register
3 Number of 1K pages addressing the DFLASH via the EPAGE register starting upwards from 0x00
1.1.6
Detailed Register Map
The detailed register map is listed in the appendix of the reference manual.
1.1.7
Part ID Assignments
The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses 0x001A and 0x001B).
The read-only value is a unique part ID for each revision of the chip. Table 1-3 shows the assigned part ID
number and Mask Set number.
The Version ID is a word located in a ?ash information row at 0x40_00E8. The version ID number
indicates a speci?c version of internal NVM variables used to patch NVM errata. The default is no patch
(0xFFFF).
Table 1-3. Assigned Part ID Numbers
Device
MC9S12XS256
MC9S12XS128
MC9S12XS64
Mask Set Number
0M05M
0M04M
1M04M
0M04M
Part ID 1
$C0C0
$C1C0
$C1C1
$C1C0
Version ID
0xFFFF
0xFFFF
0xFFFF
0xFFFF
1M04M $C1C1
0xFFFF
28
1
The coding is as follows:
Bit 15-12: Major family identi?er
Bit 11-6: Minor family identi?er
Bit 5-4: Major mask set revision number including FAB transfers
Bit 3-0: Minor — non full — mask set revision
S12XS Family Reference Manual, Rev. 1.13
Freescale Semiconductor
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